1. Field of the Invention
The present invention relates to a programmable gate array apparatus.
2. Description of the Related Art
FIG. 1 shows an example of a programmable gate array that inputs circuit information that dynamically determines operations of a circuit, to a lookup table (LUT) that determines a large number of circuit operations, a set of storage elements (hereinafter referred to as macrocells) that store outputs from the lookup table, and a programmable interconnection network (macrocells interconnection network) that connects the macrocells together.
Here, the following are collectively called context data: the circuit information stored in the LUT and determining the operations of the programmable gate array, the initial states of the storage elements storing outputs from LUT, and connection information on the interconnection network.
The circuit requires a large amount of context data because context data must be individually loaded into all macro cells mounted in the programmable gate array. A large number of macrocells are also mounted in the circuit so that layout of signal lines individually identifying the macrocells results in an increase in the size of the circuit. The context data is thus loaded by cascading the macrocells as shown in FIG. 2 and sequentially transferring the data among the macrocells.
On the other hand, this method requires a relatively long time to load the context data. Stopping the operation of the gate array during this period reduces the effective operation time and processing ability of the gate array.
Storage elements into which context data is loaded are thus provided separately from LUT. Once the storage elements are filled with context data, the data is transferred in parallel from the storage elements to LUT. This enables the stop time to be significantly reduced.
However, this method requires the programmable gate array to contain the storage elements that do not relate directly to the operations. As a result, a large part of the circuit mounted in the gate array is disadvantageously ineffectively utilized.
Cascading the macrocells enables a reduction in the number of wires required to distribute context data. However, the sequential transmission requires data to be loaded into macrocells not involved in the operations.
It has been proposed that the circuit information items in the programmable gate array (hereinafter also referred to as context data items) be dynamically replaced with one another and switched in a time division manner to equivalently implement a large-scale circuit (see, for example, Jpn. Pat. Appln. KOKAI Publication No. 11-317659).
However, since the circuit information has a large amount of data, a large overhead associated with the circuit switching may result from simple loading of the circuit information item into the gate array as required. This may degrade the processing performance of the entire circuit.
The method of storing all the contexts in the gate array reduces the switching time itself but disadvantageously increases the circuit scale of the programmable gate array itself.
As described above, the conventional technique is disadvantageous in that if the context data items in the gate array are replaced with one another so as to allow the single gate array to implement different circuits, it is impossible to reduce the time required to switch the context data items using a small number of storage elements.